openroad-flow-script.c
Open to full-time roles
Jayaram Rajgopal
Embedded Systems ·
RTL Design ·
Physical Design & VLSI
Building intelligence from silicon up.
Recent dual-degree graduate in Electrical Engineering and Computer Systems Engineering from RPI, with hands-on experience spanning embedded firmware, FPGA design, PCB layout, , physical design and machine learning. I've built FreeRTOS-based STM32 systems, custom PCBs, and real-time computer vision pipelines running on embedded hardware. I'm looking to bring that breadth to roles in embedded systems, hardware verification, silicon design or applied AI.
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Academic Background
Education
Bachelor of Science · Electrical Engineering · Computer Systems Engineering
Rensselaer Polytechnic Institute
Sep 2020 — Dec 2025
Troy, NY
- Relevant coursework: Data Structures, Intro to Algorithms, Electrical Circuits, Intro to Electronics, Microprocessor Systems, Advanced Computer Systems, Robotics, VLSI Design, Intro to Machine Learning
Additional Coursework · Electrical Engineering
Portland State University
Apr 2026 — Jun 2026
Portland, OR
- Relevant coursework: Verilog & FPGA Design, Microprocessor Interfacing & Embedded Systems
Open Source
Projects
bert-pruning-comparison.c
real-time-collision-detection.c
stop-sense.c
mcp-security-simulation.c
MCP Security Simulation
Simulates file integrity attacks against an MCP (Model Context Protocol) server, including a reference MITM proxy. Features an interactive REPL where users toggle HMAC-SHA256 cryptographic sealing on/off to compare secured vs. unsecured states in real time.
PythonHMAC-SHA256MCPMITM Proxy
vlsi-design-—-cmos-circuits.c
VLSI Design — CMOS Circuits
Designed and verified CMOS circuit schematics and layouts in Cadence Virtuoso, running DRC, LVS, and post-layout PEX simulations to validate functionality.
Cadence VirtuosoCMOSDRC/LVSSPICE
microprocessor-systems.c
Microprocessor Systems
Series of HAL and register-level projects on the STM32 in C and Assembly, covering GPIO, Timers, UART/SPI, ADC/DAC, DMA, and USB peripherals.
CAssemblySTM32LinuxGPIO / UART / I2C / SPI / USB / PWM / ADC
fpga-logic-design.c
FPGA Logic Design
Implemented and simulated core digital logic units — Full Adder, ALU, registers, and RAM — in Verilog, VHDL, and MIPS Assembly on a Xilinx Basys 3 FPGA.
VerilogVHDLMIPS AssemblyXilinxQuestaSim
Work History
Experience
AI Intern
IIT Madras Pravartak
May 2026 — Aug 2026
Chennai, India
- Ran a comparison study across various object detection models to identify the best performing model with low latency using mAP, precision, and recall
- Conducted a performance test that analyzed the various metrics of pre-trained BERT model before and after pruning
- Developed a custom a chatbot for train station customer FAQs using that uses a BERT(standard and pruned) classifier, hybrid RAG pipeline, and small-scale LLM for human-like responses
- Augmented a YOLOv26-based crowd analytics program using the OSNet Re-ID model and StrongSORT
IT and Dev Ops Intern
Siemens Digital Industries Software
Jun 2022 — Aug 2022
Wilsonville, OR
- Developed a C# and Microsoft SQL Server-based REST API web service enabling users to view and submit requests for emulation machine access.
- Enhanced website performance by optimizing the portal using Bootstrap, AJAX, and JavaScript.
Competencies
Skills
Languages
CC++C#PythonVerilogVHDLARM AssemblyBashMATLABSQL
Hardware & Embedded
ARM Cortex-M/ASTM32ESP32ArduinoRaspberry PiNvidia JetsonXilinx FPGAsPCB Design (KiCad)DMA / SPI / I2C / UART / USBVLSI Design (Cadence Virtuoso)OpenROADRTL Simulation (Icarus Verilog & QuestaSim)
AI / ML
PyTorchYOLOv8CNNs / R-CNNsTransformersScikit-learnOpenCVONNXVLMsrPPGRAG & Agentic Flows
Frameworks & Tools
CMakeMakeGitGDBDockerLinuxREST API
Always learning — this list is never complete.
Contact
I welcome inquiries regarding roles, collaborations, or technical discussions. Please feel free to reach out through any of the channels below.